 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CML Microcircuits COMMUNICATION SEMICONDUCTORS CMX7031 CMX7041 The Two-Way Radio Processor 4FSK Data Modem D/7031/41_FI2.0/1 December 2006 DATASHEET Advance Information CMX7031 / CMX7041 - FI 2.0: Baseband Data Processor with Auxiliary System Clocks, ADCs and DACs Features * 4-level FSK modem * Automatic frame sync detection * Automatic preamble, frame sync insertion * 2 x Auxiliary ADCs and 4 x Auxiliary DACs * 3 x Analogue Inputs (Mic or Discriminator) * C-BUS Serial Interface to Host Controller * 2 RF Synthesisers (CMX7031 only) * 4.8 and 9.6 kbits/s option * Raw mode, data pump * Auxiliary System Clock Outputs * Tx Outputs for Two Point or I & Q Modulation * Available in 48/64-pin LQFP & VQFN Packages * Low-power (3.0V to 3.6V) Operation * Flexible Powersave Modes * Soft decision decoding option for use with with a Vocoder DAC outputs ADC inputs 3.0V to 3.6V Modulator Discriminator RF RF Synthesiser 1 RF Synthesiser 2 CMX7031 only GPIO System Clock 1 System Clock 2 Reference Clock CMX7031 / CMX7041 The Two-Way Radio Processor Built on FirmASIC(R) technology Optional Vocoder for digital voice applications This document contains: Datasheet User Manual Host C 1 Brief Description The CMX7031/CMX7041 FI-2.0 is a half-duplex 4-level FSK modem suitable for use in PMR/LMR radios. In conjunction with a suitable host controller and radio modules, this provides the digital baseband processing to implement a radio to satisfy the requirements of ETS 102 490 and EN 301 166 or EN 300 113. The CMX7041 is identical in functionality to the CMX7031 with the exception that the two on-chip RF Synthesizers have been deleted, which enables it to be supplied in a smaller package. Continued... (c) 2006 CML Microsystems Plc 6 4FSK Radio Processor CMX7031/CMX7041 The device utilises CML's proprietary FirmASIC(R) component technology. On-chip sub-systems are configured by a Function ImageTM: this is a data file that is uploaded during device initialisation and defines the device's function and feature set. The Function ImageTM can be loaded automatically from an external EEPROM or from a host Controller over the built-in C-BUS serial interface. The device's functions and features can be enhanced by subsequent Function ImageTM releases, facilitating in-the-field upgrades. The same device can be loaded with FI-1.x to provide Analogue functionality including simultaneous processing of subaudio and inband signalling and audio band processing (with frequency inversion scrambling, companding and pre- or de-emphasis). Other features include two Auxiliary ADC channels with four selectable inputs and up to four auxiliary DAC interfaces (with an optional RAMDAC on the first DAC output, to facilitate transmitter power ramping). The device has flexible powersaving modes and is available in both LQFP and VQFN packages. Note that text shown in pale grey indicates features that will be supported in future versions of the device. This Datasheet is the first part of a two-part document comprising Datasheet and User Manual: the User Manual can be obtained by registering your interest in this product with your local CML representative. (c) 2006 CML Microsystems Plc Page 2 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 CONTENTS Section 1 2 3 4 5 6 Page Brief Description.....................................................................................................................1 Block Diagram ........................................................................................................................6 Signal List................................................................................................................................7 External Components ..........................................................................................................10 PCB Layout Guidelines and Power Supply Decoupling...................................................13 General Description .............................................................................................................15 6.1 CMX7031/CMX7041 FI 2.0 Features ........................................................................15 6.2 Introduction................................................................................................................17 6.2.1 Modulation ...........................................................................................................17 6.2.2 Framing................................................................................................................19 6.2.3 FEC and Coding ..................................................................................................19 6.2.4 Voice Coding .......................................................................................................19 6.2.5 Radio Performance Requirements ......................................................................19 Detailed Descriptions...........................................................................................................20 7.1 Xtal Frequency ..........................................................................................................20 7.2 Host Interface ............................................................................................................20 7.2.1 C-BUS Operation.................................................................................................20 7.3 Function ImageTM Loading ........................................................................................22 7.3.1 FI Loading from Host Controller ..........................................................................22 7.3.2 FI Loading from EEPROM...................................................................................24 7.4 Device Control ...........................................................................................................25 7.4.1 General Notes .....................................................................................................25 7.4.2 Interrupt Operation ..............................................................................................25 7.4.3 Signal Routing .....................................................................................................25 7.4.4 Modem Control ....................................................................................................26 7.4.5 Tx Mode...............................................................................................................27 7.4.6 Rx Mode ..............................................................................................................28 7.4.7 Other Modem Modes...........................................................................................29 7.4.8 Data Transfer.......................................................................................................29 7.5 Squelch Operation.....................................................................................................30 7.6 GPIO Pin Operation...................................................................................................30 7.7 Audio Tone Facility ....................................................................................................30 7.8 Auxiliary ADC Operation ...........................................................................................31 7.9 Auxiliary DAC / RAMDAC Operation.........................................................................31 7.10 Digital System Clock Generators ..............................................................................32 7.10.1 System Clock Operation .....................................................................................34 7.10.2 Main Clock Operation .........................................................................................34 7.11 Signal Level Optimisation ..........................................................................................34 7.11.1 Transmit Path Levels ..........................................................................................34 7.11.2 Receive Path Levels ...........................................................................................34 7.12 Tx Spectrum Plots .....................................................................................................34 7 (c) 2006 CML Microsystems Plc Page 3 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.13 8 C-BUS Register Summary ........................................................................................36 Performance Specification ..................................................................................................37 8.1 Electrical Performance ..............................................................................................37 8.1.1 Absolute Maximum Ratings.................................................................................37 8.1.2 Operating Limits ..................................................................................................38 8.1.3 Operating Characteristics ....................................................................................39 8.1.4 Parametric Performance......................................................................................45 8.2 C-BUS Timing............................................................................................................46 8.3 Packaging..................................................................................................................48 Page Table Table 1 Xtal/Clock Frequency Settings for Program Block 3........................................................ 20 Table 2 BOOTEN Pin States ........................................................................................................ 22 Table 3 Modem Mode Selection ................................................................................................... 26 Table 4 Modem Control Selection.................................................................................................. 26 Table 5 C-BUS Data Registers ..................................................................................................... 30 Table 6 C-BUS Registers.............................................................................................................. 36 Figure Page Figure 1 CMX7031 / 7041 Block Diagram ....................................................................................... 6 Figure 3 CMX7031 Recommended External Components ........................................................... 10 Figure 4 CMX7041 Recommended External Components ........................................................... 11 Figure 5 CMX7031 Power Supply and De-coupling ...................................................................... 13 Figure 6 CMX7041 Power Supply and De-coupling ...................................................................... 14 Figure 7 Digital Voice Rx and Tx Blocks........................................................................................ 16 Figure 8 4FSK PRBS Waveform.................................................................................................... 17 Figure 9 Modulation Characteristics .............................................................................................. 18 Figure 10 C-BUS Transactions ...................................................................................................... 21 Figure 11 FI Loading from Host ..................................................................................................... 23 Figure 12 FI Loading from EEPROM ............................................................................................. 24 Figure 13 Tx Data Flow.................................................................................................................. 28 Figure 14 Rx Data Flow ................................................................................................................. 29 Figure 15 Digital Clock Generation Schemes................................................................................ 32 Figure 16 Tx Modulation Spectra - 4800bps.................................................................................. 35 Figure 17 Tx Modulation Spectra - 9600bps.................................................................................. 35 Figure 18 C-BUS Timing................................................................................................................ 46 Figure 19 Mechanical outline for 64-pad VQFN (Q1) .................................................................... 48 Figure 20 Mechanical outline for 64-pin LQFP (L9)....................................................................... 48 Figure 21 Mechanical Outline of 48-pin VQFN (Q3)...................................................................... 49 Figure 22 Mechanical Outline of 48-pin LQFP (L4) ....................................................................... 49 Information in this data sheet should not be relied upon for final product design. It is always recommended that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com]. Note: This product is in development: Changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. (c) 2006 CML Microsystems Plc Page 4 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 Information in this data sheet should not be relied upon for final product design. (c) 2006 CML Microsystems Plc Page 5 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 2 Block Diagram Transmit Functions Output 1 Data Modulator Tx data buffer Raw data 4FSK modulator Sinc filter RRC filter Tx Modulator mode Output 2 MOD 1 O/P MOD 2 O/P Tone generator Audio out Receive Functions Mic I/P VBias ALT I/P Analogue Routing VBias Disc I/P Data Demodulator Rx Eye test mode RRC filter Sinc-1 filter AFSD 4FSK Demodulator Raw data Rx data buffer VBias Auxiliary Functions System clock 1 GPIO 1/Tx Enable GPIO GPIO 2/Rx Enable GPIO A GPIO B GPIO (CMX7041 only) System clock 2 Clock O/P 2 Clock O/P 1 Auxiliary System Clocks FI Configured I/O RF I/P1 Synthesiser 1 Out CP1 DAC 1 DAC 2 DAC 3 DAC 4 DAC 1 DAC 2 DAC 3 Ramp profile RAM ISet 1 RF I/P2 DAC 4 Auxiliary DACs Internal signal Thresholds Synthesiser 1 Out CP2 ISet 2 RFVdd CPVdd ADC I/P 1 ADC I/P 2 ADC I/P 3 ADC I/P 4 MUX ADC 1 Averaging Thresholds ADC 2 Averaging RF Synthesisers (CMX7031 only) RFVss RFClk Auxiliary Multiplexed ADCs System Control EPSI EPSClk EPSO EPCSN Bias Bias EEPROM Interface Boot Control Main clock PLL Registers Crystal oscillator Power control C-BUS Interface IRQ Reply Data CSN CMD Data Serial Clk AVdd Boot En1 Boot En2 VBias DVdd Figure 1 CMX7031 / 7041 Block Diagram (c) 2006 CML Microsystems Plc Page 6 Clk/Xtal XtalN AVss VDec DVss D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 3 Signal List CMX7031 CMX7041 64-pin 48-pin Q1 / L9 Q3 / L4 Signal Name Type Description C-BUS: A 'wire-ORable' output for connection to the Interrupt Request input of the host. Pulled down to VSS(D) when active and is high impedance when inactive. An external pull-up resistor (R1) is required. RF Synthesizer #1 negative input. RF Synthesizer #1 positive input. The negative supply rail (ground) for the RF synthesizers. 1st Charge Pump output. 1st Charge Pump Current Set input. The 2.5V positive supply rail for the RF synthesizers. This should be decoupled to RFVss by a capacitor mounted close to the device pins. RF Synthesizer #2 negative input. RF Synthesizer #2 positive input. The negative supply rail (ground) for the 2nd RF synthesizer. 2nd Charge Pump output. 2nd Charge Pump Current Set input. The 3.3V positive supply rail for the RF charge pumps. This should be decoupled to RFVss by a capacitor mounted close to the device pins. RF Clock Input (common to both synthesizers)1. Reserved - do not connect this pin. Reserved - do not connect this pin. Reserved - do not connect this pin. Internally generated 2.5V digital supply voltage. Must be decoupled to DVss by capacitors mounted close to the device pins. No other connections allowed, except for optional connection to RFVdd. General Purpose I/O pin (RxENA) General Purpose I/O pin (CMX7041 only) General Purpose I/O pin (CMX7041 only) Synthesized Digital System Clock Output 1. Digital Ground. Reserved - do not connect this pin. General Purpose I/O pin (TxENA) 1 8 IRQN OP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 - RF1 - RF1 + RFVss CP1OUT ISET1 RFVdd RF2 - RF2 + RFVss CP2OUT ISET2 CHARGE PUMP RF CLOCK - IP IP PWR OP IP PWR IP IP PWR OP IP PWR IP NC NC NC 18 9 VDEC PWR 19 20 21 22 23 1 10 11 12 13 14 15 GPIO1 GPIOA GPIOB SYS CLK 1 DVss GPIO2 BI BI BI OP PWR NC BI To minimise crosstalk, this signal should be connected to the same clock source as XTAL / CLOCK input. By default, this is connected internally at power-on, alternatively, this may be achieved by connecting the pin to the XTALN output when a 19.2MHz source is in use. (c) 2006 CML Microsystems Plc Page 7 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 CMX7031 CMX7041 64-pin 48-pin Q1 / L9 Q3 / L4 24 25 26 27 28 29 30 31 32 16 17 18 19 20 21 22 23 24 Signal Name DISC DISCFB ALT ALTFB MICFB MICIN AVss MOD1 MOD2 Type IP OP IP OP OP IP PWR OP OP Description Channel 1 inverting input. Channel 1 input amplifier feedback. Channel 2 inverting input. Channel 2 input amplifier feedback. Channel 3 input amplifier feedback Channel 3 inverting input Analog Ground. Modulator 1 output. Modulator 2 output. Internally generated bias voltage of about AVdd/2, except when the device is in `Powersave' mode when VBIAS will discharge to AVss. Must be decoupled to AVss by a capacitor mounted close to the device pins. No other connections allowed. Reserved for future use2. Auxiliary ADC input 1 Auxiliary ADC input 2 Auxiliary ADC input 3 Auxiliary ADC input 4 Analog +3.3V supply rail. Levels and thresholds within the device are proportional to this voltage. This pin should be decoupled to AVss by capacitors mounted close to the device pins. Auxiliary DAC output 1 / RAMDAC. Auxiliary DAC output 2. Analog Ground. Auxiliary DAC output 3. Auxiliary DAC output 4. Digital Ground. Internally generated 2.5V supply voltage. Must be decoupled to DVss by capacitors mounted close to the device pins. No other connections allowed, except for the optional connection to RFVdd. input from the external clock source or Xtal The output of the on-chip Xtal oscillator inverter. NC if external Clock used. 33 25 VBIAS OP 34 35 36 37 38 26 27 28 29 30 AUDIO OUT AUXADC1 AUXADC2 AUXADC3 AUXADC4 OP IP IP IP IP 39 31 AVdd PWR 40 41 42 43 44 - 32 33 34 35 36 37 AUXDAC1 AUXDAC2 AVss AUXDAC3 AUXDAC4 DVss OP OP PWR OP OP PWR 45 38 VDEC PWR 46 47 2 39 40 XTAL / CLOCK XTALN IP OP The AUDIO OUT pin is not currently used in this FI, however it has been included here for compatibility with FI 1.x (c) 2006 CML Microsystems Plc Page 8 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 CMX7031 CMX7041 64-pin 48-pin Q1 / L9 Q3 / L4 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 Signal Name DVdd COMMAND DATA REPLY DATA DVss SERIAL CLOCK SYS CLK 2 CSN EPSI EPSCLK EPSO EPSCSN BOOTEN1 BOOTEN2 DVss Type Description Digital +3.3V supply rail. This pin should be decoupled to DVss by capacitors mounted close to the device pins. C-BUS: Serial data input from the C. C-BUS: A 3-state C-BUS serial data output to the C. This output is high impedance when not sending data to the C. Reserved - do not connect this pin. Digital Ground. Reserved - do not connect this pin. C-BUS: The C-BUS serial clock input from the C. Synthesized Digital System Clock Output 2. C-BUS: The C-BUS chip select input from the C Reserved - do not connect this pin. EEPROM Serial Interface: SPI bus Output. EEPROM Serial Interface: SPI bus Clock. PWR IP TS OP NC PWR NC IP OP IP NC OP OP IP+PD EEPROM Serial Interface: SPI bus Input. OP IP+PD IP+PD PWR EEPROM Serial Interface: SPI bus Chip Select. Used in conjunction with BOOTEN2 to determine the operation of the bootstrap program. Used in conjunction with BOOTEN1 to determine the operation of the bootstrap program. Digital Ground. Notes: IP OP BI TS OP PWR NC = = = = = = Input (+ PU/PD = internal pullup / pulldown resistor) Output Bidirectional 3-state Output Power Connection No Connection - should NOT be connected to any signal. (c) 2006 CML Microsystems Plc Page 9 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 4 External Components Figure 3 CMX7031 Recommended External Components (c) 2006 CML Microsystems Plc Page 10 D/7031/41_FI2.0/1 4FSK Radio Processor CBUS CMX7031/CMX7041 C1 DVSS COMMAND DATA SERIAL CLOCK DVDD X1 C2 C3 + REPLY DATA SYSCLK2 DVDD DVSS XTAL/CLK VDEC XTALN CSN C4 n/c DVSS EPSI EPSCLK EPSO DVDD R1 AUX DAC 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AUX DAC 3 AVSS AUX DAC 2 AUX DAC 1 AVDD AUX ADC 4 AUX ADC 3 AUX ADC 2 AUX ADC 1 AUDIO OUT VBIAS C7 R2 C5 C6 AVDD AVSS EPSCSN BOOTEN1 BOOTEN2 DVSS IRQN Aux DAC CMX7041L4 DVSS VDEC GPIO1 GPIOA GPIOB Aux ADC Audio SYSCLK1 MOD 1 DISC FB ALT FB MIC FB MOD 2 GPIO2 DVSS AVSS DISC MIC ALT AVSS R3 AVSS MOD 2 AVSS C8 + C24 C23 DVSS DVSS DVSS C12 R6 R5 C14 R8 C16 R10 AVSS R4 MOD 1 R7 R9 C9 C11 C13 C15 AVDD AVSS DVDD DISC + + ALT MIC C17 C18 C19 C20 C21 C22 AVSS AVSS AVSS DVSS DVSS DVSS Figure 4 CMX7041 Recommended External Components (c) 2006 CML Microsystems Plc Page 11 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 100k 100k 100k 100k See note 2 100k See note 3 100k See note 4 100k C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 18pF 18pF 10nF 10F 1nF 100pF 100nF 100pF 100pF not used C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 See note 5 100pF See note 5 100pF See note 5 200pF 10F 10nF 10nF 10F C21 C22 C23 C24 C25 C26 X1 10nF 10nF 10F 10nF 10nF 10F 6.144MHz See note 1 Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 1. X1 can be a crystal or an external clock generator; this will depend on the application. The tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. By default, a 6.144MHz crystal is assumed, other values could be used if the various internal clock dividers are set to appropriate values. 2. R5 should be selected to provide the desired dc gain (assuming C11 is not present) of the discriminator input, as follows: GAINDisc = 100k / R5 The gain should be such that the resultant output at the DISCFB pin is within the discriminator input signal range specified in 7.11.2. 3. R7 should be selected to provide the desired dc gain (assuming C13 is not present) of the alternative input as follows: GAINAlt = 100k / R7 The gain should be such that the resultant output at the ALTFB pin is within the alternative input signal range specified in 7.11. R9 should be selected to provide the desired dc gain (assuming C15 is not present) of the microphone input as follows: GAINMic = 100k / R9 The gain should be such that the resultant output at the MICFB pin is within the microphone input signal range specified in 7.11.1. For optimum performance with low signal microphones, an additional external gain stage may be required. C11, C13 and C15 should be selected to maintain the lower frequency roll-off of the microphone, alternative and discriminator inputs as follows: C11 1.0F x GAINDisc C13 1.0F x GAINAlt 6. C15 30nF x GAINMic ALT and ALTFB connections allow the user to have a second discriminator or microphone input. Component connections and values are as for the respective DISC and MIC networks. If this input is not required, the ALT pin should be connected to AVss. 4. 5. (c) 2006 CML Microsystems Plc Page 12 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 5 PCB Layout Guidelines and Power Supply Decoupling Figure 5 CMX7031 Power Supply and De-coupling (c) 2006 CML Microsystems Plc Page 13 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 DVDD + Digital Ground Plane DVSS DVSS C20 C21 C22 DVSS DVSS DVSS C3 DVDD VDEC + C4 DVSS 1 2 3 4 5 DVSS DVSS VDEC 6 7 8 9 10 11 12 13 14 15 16 17 18 VBIAS C7 AVSS AVSS AVDD CMX7041L4 AVDD + C17 C18 C19 AVSS AVSS AVSS DVSS + AVSS AVSS AVSS C24 C23 Analogue Ground Plane DVSS DVSS DVSS Figure 6 CMX7041 Power Supply and De-coupling Component Values as per Figure 4. Notes: It is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the CMX7041 and the supply and bias de-coupling capacitors. The de-coupling capacitors C3, C7, C18, C19, C21, C22, C24 and C25 should be as close as possible to the CMX7031/CMX7041. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVSS and DVSS supplies in the area of the CMX7031/CMX7041, with provision to make links between them, close to the CMX7041. Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with a high input impedance buffer. The single ended microphone input and audio output must be ac coupled (as shown), so that their return paths can be connected to AVSS without introducing dc offsets. Further buffering of the audio output is advised. The crystal, X1, may be replaced with an external clock source. (c) 2006 CML Microsystems Plc Page 14 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 6 6.1 General Description CMX7031/CMX7041 FI 2.0 Features The CMX7031 / CMX7041 FI 2.0 is intended for use in half duplex digital two way mobile radio equipment using 4-level FSK modulation at 4800 or 9600 bits/s. The ability to re-load the device with FI 1.x allows the same platform to offer backwards compatibility with existing analogue radio systems. A flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals. The device includes a crystal clock generator, with buffered output, to provide a common system clock if required. A block diagram of the device is shown in Figure 1. The signal processing blocks can be routed from any of the three audio / discriminator input pins. Tx Functions: o 72bit Tx data buffer o Automatic Preamble, Frame Sync insertion simplifies host control o 4 level FSK modulator o RRC filtering o RAMDAC operation o TxENA hardware signal o Two-point or I & Q modulation outputs Rx Functions: o Demodulator input with input amplifier and programmable gain adjustment o 72bit Rx data buffer o Automatic Frame Sync detection simplifies host control o Selectable squelch source o RRC filtering o 4 level FSK de-modulator o Hard or Soft data options o RxENA hardware control signal Auxiliary Functions: o 2 programmable system clock outputs o 2 auxiliary ADCs with four selectable input paths o 4 auxiliary DACs, one with built-in programmable RAMDAC o Audio Tone generator o 2 RF PLL's (CMX7031 only) Interface: o o o o o Optimised C-BUS (4 wire high speed synchronous serial command / data bus) interface to host for control and data transfer Open drain IRQ to host Two GPIO pins (CMX7041 only) EEPROM boot mode C-BUS (host) boot mode (c) 2006 CML Microsystems Plc Page 15 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 Squelch Rx_ena Tx_ena RF Section Disc TXmod1 TXmod2 PAramp modem cbus clk cbus datain cbus csn0 cbus dataout coding CMX7031 / CMX7041 protocol Host Mic Spkr spi port Audio Codec Vocoder csn1 Squelch Rx_ena Tx_ena RF Section Disc TXmod1 TXmod2 PAramp modem cbus clk cbus datain cbus csn0 cbus dataout coding CMX7031 / CMX7041 protocol Host Mic Spkr spi port Audio Codec Vocoder csn1 Figure 7 Digital Voice Rx and Tx Blocks The paralleling of the Mic and Spkr connections is required if the CMX7031/CMX7041 is to provide full analogue PMR functionality, as provided in FI 1.x. The Audio Codec and Voice Codec functionality can also be provided by a suitable Vocoder product such as CML's RALCWI Vocoder CMX618 or DVSI's AMBE 2020 plus an Audio Codec chip. The AuxADC can be used to detect the Squelch signal from the RF section, while still retaining a significant degree of power saving within the CMX7031/CMX7041 and obviating the need to wake the host up un-necessarily. The use of the programmable thresholds allows for user selection of squelch threshold settings programmed from the host. Preamble detection may be useful in situations where the channel is shared with an analogue system and allow the host to configure itself to receive either modulation. Before any data is transmitted over the air, the initial data needs to be loaded from the host into the CBUS TxData registers. The CMX7031/CMX7041 can be transmitting data from the modem while at the (c) 2006 CML Microsystems Plc Page 16 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 same time receiving the next data block from the host. In Rx, the host needs to understand that there will be a delay from receiving the data over the air to the data arriving at its input while the CMX7031/CMX7041 filters and demodulates the incoming signal before presenting it to the output buffer. These buffering and coding processes will add delays to the overall data stream, which will add to the delays in transferring the data between the CMX7031/CMX7041 and the host and subsequently from the host to the Voice Codec. In order to offer the best performance, the demodulator can be set to output soft-decision data compatible with the CMX618 and DVSI AMBE 2020 Vocoders during reception of voice payload data. This mode increases the Rx data rates over the host C-BUS by a factor of 4. The soft decision data is transferred as 4-bits, log-likelihood encoded. This modem can run at either 4800bps or 9600bps. In the 9600bps mode, this will occupy a 12.5kHz bandwidth RF channel. 6.2 Introduction This uses a 4FSK modulation scheme with an over-air bit rate of 4800bps (ie: 2400 symbols per second) compatible with the limits set in EN 301 166. For use on 12.5kHz channel spacing systems, the CMX7031/CMX7041 also offers a 9600bps (4800symbols per second) mode where EN 300 113 applies. See www.etsi.org for details of these standards. 6.2.1 Modulation The 4 level FSK scheme running at 2400 symbols/s (4800 bits/s) can be used in order to fit inside a 6.25kHz channel bandwidth. RRC filters are implemented at both Tx and Rx. This mode uses a "deviation index" of 0.29 and a filter "alpha" of 0.2. The maximum frequency error is +/- 625Hz and can adapt to a maximum time base clock drift of 2ppm over the duration of a 180s (maximum) burst. Figure 9 is an extract from the ETS 102 490 standard showing the basic parameters of the 4FSK modulation system, symbol mapping and filtering requirements. The 4800 symbols/s (9600 bits/s) mode is essentially the same, but with the timings modified by a factor of two. Figure 8 4FSK PRBS Waveform (c) 2006 CML Microsystems Plc Page 17 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 Figure 9 Modulation Characteristics (c) 2006 CML Microsystems Plc Page 18 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 6.2.2 Framing The CMX7031/CMX7041 uses a 72bit preamble and a 24 bit Frame Synch. The CMX7031/CMX7041 can look for two different Frame Synch patterns concurrently. Subsequent Frame Syncs within the data burst are used to make any timing corrections that maybe required. Both the preamble and Frame Synch's are user-programmable, see User Manual sections 10.1.25 bit 1 and 10.2.1 Once a valid header has been received, and the initial timing established, timing corrections can be derived from the following embedded synch patterns to cater for up to 180s of data and to recover from fading. 6.2.3 FEC and Coding The CMX7031/CMX7041 does not implement any FEC, coding or interleaving. 6.2.4 Voice Coding The CML CMX618 and the DVSI AMBE 2020 are suitable devices for this application. In both cases, the Voice Decoder (in Rx mode) requires 4-bit log-likelihood encoded soft coded data from the modem. This increases the data rate by a factor of 4 in the Rx state. 6.2.5 Radio Performance Requirements It should be noted that the CMX7031/CMX7041 is designed to process a demodulated 4FSK signal from a limiter / discriminator source, therefore for optimum performance, it is important that the demodulated signal is not significantly degraded by narrow filters and / or group delay distortion. (c) 2006 CML Microsystems Plc Page 19 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7 7.1 Detailed Descriptions Xtal Frequency The CMX7031/CMX7041 is designed to work with a Xtal or external frequency source of 6.144MHz. If this default configuration is not used, then Program Register Block 3 must be loaded with the correct values to ensure that the device will work to specification with the user specified clock frequency. A table of common values can be found in Table 1. Note the maximum Xtal frequency is 12.288MHz, although an external clock source of up to 24MHz can be used. The register values in Table 1 are shown in hex, the default settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. The new P3.2-3 settings take effect following the write to P3.3 (the settings in P3.4-7 are implemented on a change to Rx or Tx mode). Table 1 Xtal/Clock Frequency Settings for Program Block 3 Program Register External frequency source (MHz) 3.579 P3.2 GP Timer P3.3 P3.4 Ref clk divide 6.144 $0018 $0088 $0040 $0200 $0140 $0808 9.0592 $0018 $010F $00C6 $0370 $0140 $0808 12.0 $0019 $010F $007D $0200 $0140 $0808 12.8 $0019 $0110 $00C8 $0300 $0140 $0808 16.368 $0018 $0095 $0155 $0400 $0140 $0808 16.8 $0019 $0115 $015E $0400 $0140 $0808 19.2 $0018 $0099 $00C8 $0200 $0140 $0808 $0017 $0085 $0043 $0398 $0140 $0808 Idle Rx or Tx VCO output and AUX clk divide P3.5 P3.6 P3.7 PLL clk divide VCO output and AUX clk divide Internal ADC / DAC clk divide 7.2 Host Interface A serial data interface (C-BUS) is used for command, status and data transfers between the CMX7031/CMX7041 and the host C; this interface is compatible with microwire, SPI. Interrupt signals notify the host C when a change in status has occurred and the C should read the status register across the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 7.4.2. 7.2.1 C-BUS Operation This block provides for the transfer of data and control or status information between the CMX7031/CMX7041's internal registers and the host C over the C-BUS serial interface. Each transaction consists of a single Address byte sent from the C which may be followed by one or more Data byte(s) sent from the C to be written into one of the CMX7031/CMX7041's Write Only Registers, or one or more data byte(s) read out from one of the CMX7031/CMX7041's Read Only Registers, as illustrated in Figure 10. Data sent from the C on the Command Data line is clocked into the CMX7031/CMX7041 on the rising edge of the Serial Clock input. Reply Data sent from the CMX7031/CMX7041 to the C is valid when the Serial Clock is high. The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with most common C serial interfaces and may also be easily implemented with general purpose C I/O pins controlled by a simple software routine. The number of data bytes following an Address byte is dependent on the value of the Address byte. The most significant bit of the address or data are sent first. For detailed timings see section 8.2. (c) 2006 CML Microsystems Plc Page 20 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 C-BUS Write: See Note 1 CSN Serial_Clock CMD_DATA 7 MSB See Note 2 6 5 4 3 2 1 0 LSB 7 MSB 6 ... 0 LSB 7 MSB ... 0 LSB Address / Command byte REPLY_DATA High Z state Upper 8 bits Lower 8 bits C-BUS Read: See Note 2 CSN Serial_Clock CMD_DATA 7 MSB 6 5 4 3 2 1 0 LSB Address byte REPLY_DATA High Z state Upper 8 bits 7 MSB Lower 8 bits 7 MSB 6 ... 0 LSB ... 0 LSB Data value unimportant Repeated cycles Either logic level valid (and may change) Either logic level valid (but must not change from low to high) Figure 10 C-BUS Transactions Notes: 1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset). 2. For single byte data transfers only the first 8 bits of the data are transferred. 3. The CMD_DATA and REPLY_DATA lines are never active at the same time. The Address byte determines the data direction for each C-BUS transfer. 4. The Serial_Clock input can be high or low at the start and end of each C-BUS transaction. 5. The gaps shown between each byte on the CMD_DATA and REPLY_DATA lines in the above diagram are optional, the host may insert gaps or concatenate the data as required. (c) 2006 CML Microsystems Plc Page 21 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.3 Function ImageTM Loading The Function ImageTM (FI), which defines the operational capabilities of the device, may be obtained from the CML website, following registration, along with the appropriate Device Activation Codes and checksum values. This is in the form of a 'C' header file which can be included into the host controller software or programmed into an external EEPROM. The maximum possible size of Function ImageTM is 46 kbytes, although a typical FI will be less than this. Note that the BOOTEN pins are only read at poweron or following a C-BUS General Reset and must remain stable throughout the FI loading process. Once the FI load has completed, the BOOTEN pins are ignored by the CMX7031 until the next power-up or CBUS General Reset. The BOOTEN pins are both fitted with internal 100k (approx.) pull down resistors. For C-BUS load operation, both pins should be pulled high by connecting them to DVDD either directly or via a 4k7 resistor (see Table 2). For EEPROM load, only BOOTEN1 needs to be pulled high in a similar manner, however, if it is required to program the EEPROM in-situ from the host, either a jumper to DVDD or a link to a host I/O pin should be provided to pull BOOTEN2 high when required (see Table 2). Once the FI has been loaded, the CMX7031/CMX7041 performs these actions:(1) (2) (3) (4) (5) the product identification code ($7031 or $7041) is reported in C-BUS register $C5 the FI version code is reported in C-BUS register $C9 the two 32-bit FI checksums are reported in C-BUS register pairs $A9, $AA and $B8, $B9 the device waits for the host to load the 32-bit Device Activation Code to C-BUS register $C8 once activated, the device initialises fully, enters idle mode and becomes ready for use. The checksums can be verified against the published values to ensure that the FI has loaded correctly. Once the FI has been activated, the checksum, product identification and version code registers are cleared and these values are no longer available. If an invalid activation code is loaded, the device will report the value $DEAD in register $A9 and become unresponsive to all further host commands (including General Reset). Both the Device Activation Code and the checksum values are available from the CML Technical Portal. Table 2 BOOTEN Pin States C-BUS Host load reserved EEPROM load No FI load BOOTEN2 1 1 0 0 BOOTEN1 1 0 1 0 Note: In the rare event that a General Reset needs to be issued without the requirement to re-load the FI, the BOOTEN pins must both be cleared to '0' before issuing the Reset command. The Checksum values will be reported and the Device Activation code will need to be sent in a similar manner as that shown in Figure 12. There will not be any FI loading delay. This assumes that a valid FI has been previously loaded and that Vdd has been maintained throughout the reset to preserve the data. 7.3.1 FI Loading from Host Controller The FI can be included into the host controller software build and downloaded into the CMX7031/CMX7041 at power-up over the C-BUS interface. The BOOTEN pins must be set to the C-BUS load configuration, the CMX7031/CMX7041 powered up and placed into Program Mode, the data can then be sent directly over the C-BUS to the CMX7031/CMX7041. (c) 2006 CML Microsystems Plc Page 22 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 BOOTEN2=1 BOOTEN1=1 Power-up / Reset CMX7041 Send Start Block 1 Address (DB1_ptr) to C-Bus $B6 Send Block 1Length (DB1_len) to C-Bus $B7 Wait for C-Bus $C6 bit 0 to be set to 1 Send $0001 to C-Bus $C8 Wait for C-Bus $C6 bit 0 to be set to 1 Send next data to C-Bus $C8 Send Start Block 2 Address (DB2_ptr) to C-Bus $B6 Send Block 2 Length (DB2_len) to C-Bus $B7 Wait for C-Bus $C6 bit 0 to be set to 1 Send $0001 to C-Bus $C8 Wait for C-Bus $C6 bit 0 to be set to 1 Send next data to C-Bus $C8 Send Start Block 3 Address (ACTIVATE_ptr) to C-Bus $B6 Send Block 3 Length (ACTIVATE_len) to C-Bus $B7 Wait for C-Bus $C6 bit 0 to be set to 1 Send $0001 to C-Bus $C8 Wait for C-Bus $C6 bit 0 to be set to 1 Verify Checksum values in $A9, $AA and $B8, $B9 note: BOOTEN1 and BOOTEN2 may be changed at this point, if required Send Device Activation Code hi to $C8 Wait for C-Bus $C6 bit 0 to be set to 1 Vdd Send Device Activation Code lo to $C8 Wait for C-Bus $C6 bit 0 to be set to 1 BOOTEN1 BOOTEN2 CMX7041 is now ready for use Figure 11 FI Loading from Host The download time is limited by the clock frequency of the C-BUS, with a 5MHz SCLK, it should take less than 500ms to complete. (c) 2006 CML Microsystems Plc Page 23 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.3.2 FI Loading from EEPROM The FI must be converted into a format for the EEPROM programmer (normally Intel Hex) and loaded into the EEPROM either by the host or an external programmer. The CMX7031/CMX7041 needs to have the BOOTEN pins set to EEPROM load, and then on power-on, or following a C-BUS General Reset, the CMX7031/CMX7041 will automatically load the data from the EEPROM without intervention from the host controller. BOOTEN2=0 BOOTEN1=1 Power-up / Reset CMX7041 Wait for C-Bus $C6 bit 0 to be set to 1 Verify Checksum values in $A9, $AA and $B8, $B9 note: BOOTEN1 and BOOTEN2 may be changed at this point, if required Send Device Activation Code hi to $C8 Wait for C-Bus $C6 bit 0 to be set to 1 Vdd Send Device Activation Code lo to $C8 Wait for C-Bus $C6 bit 0 to be set to 1 BOOTEN1 BOOTEN2 Jumper for programming EEPROM (if required) CMX7041 is now ready for use Figure 12 FI Loading from EEPROM The CMX7031/CMX7041 has been designed to function with Atmel AT25HP512 devices, however other manufacturers parts may also be suitable. The time taken to load the FI is dependant on the Xtal frequency, with a 6.144MHz Xtal, it should load in less than 1 second. (c) 2006 CML Microsystems Plc Page 24 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.4 Device Control The CMX7031/CMX7041 can be set into the relevant mode to suit its environment. These modes are described in the following sections and are programmed over the C-BUS: either directly to operational registers or, for parameters that are not likely to change during operation, via the Programming register ($C8). For basic operation, enable the relevant hardware sections via the Power Down Control register, set the appropriate mode registers to the desired state, select the required Signal Routing, and then use the Mode Control register to place the device into Rx or Tx mode. To conserve power when the device is not actively processing a signal, place the device into Idle mode. Additional Power-saving can be achieved by disabling the unused hardware blocks, however, care must be taken not to disturb any sections that are automatically controlled. Note that the BIAS block must be enabled to allow any of the Input or Output blocks to function. See: o o o Power Down Control - $C0 write Modem Control - $C1 write Modem Config - $C7 write 7.4.1 General Notes In normal operation, the most significant registers, in addition to the TxData and RxData blocks, are: o o o o o Modem Control - $C1 write Status - $C6 read Analogue Output Gain - $B0 write Input Gain and Output Signal Routing - $B1 write AuxData Write - $C2 write Setting the Mode register to either Rx or Tx will automatically increase the internal clock speed to its operational speed, whilst setting the Mode register to IDLE will automatically return the internal clock to a lower (powersaving) speed. To access the Program Blocks (through the Programming register, $C8) the device MUST be in IDLE mode. Under normal circumstances the CMX7031/CMX7041 manages the Main Clock Control automatically, using the default values loaded in Program Block 3. 7.4.2 Interrupt Operation The CMX7031/CMX7041 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and the IRQ Mask bit (bit 15) are both set to 1. The IRQ bit is set when the state of the interrupt flag bits in the Status register change from a 0 to 1 and the corresponding mask bit(s) in the Interrupt Mask register is(are) set. Enabling an interrupt by setting a mask bit (01) after the corresponding Status register bit has already been set to 1 will also cause the IRQ bit to be set. All interrupt flag bits in the Status register, except the Programming Flag (bit 0), are cleared and the interrupt request is cleared following the command/address phase of a C-BUS read of the Status register. The Programming Flag bit is set to 1 only when it is permissible to write a new word to the Programming register. See: o o Status - $C6 read Interrupt Mask - $CE write 7.4.3 Signal Routing The CMX7031/CMX7041 offers a flexible routing architecture, with three signal inputs, and a choice of two modulator configurations (to suit 2-point modulation or I & Q schemes) and a single Audio output. See: o o Input Gain and Output Signal Routing - $B1 write Modem Control - $C1 write (c) 2006 CML Microsystems Plc Page 25 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 o Modem Config - $C7 write The analogue gain / attenuation of each input and output can be set individually, with additional Fine Attenuation control available via the Programming registers. See: o o Analogue Output Gain - $B0 write Input Gain and Output Signal Routing - $B1 write In common with other FI's developed for the CMX7031/CMX7041, this device is equipped with two signal processing paths. However, in this implementation of the FI, Input 2 is not currently used and so should not be enabled. Input 1 should be routed to either of the three input sources (ALT, DISC or MIC). Output 1 and 2 are used to provide either 2-point or I&Q signals and should be routed to MOD1 and MOD2 as required. 7.4.4 Modem Control The CMX7031 operates in one of three modes: o o o IDLE Rx Tx At power-on or following a Reset, the device will automatically enter IDLE mode, which allows for the maximum power-saving whilst still retaining the capability of monitoring the AuxADC inputs (if enabled). It is only possible to write to the Programming register whilst in IDLE mode. See: o Modem Control - $C1 write GPIO1 and 2 pins reflect bits 0 and 1 of the Modem Control register, as shown in Table 3. These can be used to drive external hardware without the host having to intervene. The CMX7041 also has two additional GPIO pins that are programmable under host control. Table 3 Modem Mode Selection Modem Control ($C1) b1-0 00 01 10 11 Modem Mode Idle - low power mode Rx mode Tx mode reserved GPIO2 1 1 0 1 GPIO1 1 0 1 1 Table 4 Modem Control Selection 4FSK Modem Control ($C1) b7-4 0000 0001 0010 0011 0100 0101 0110 0111 1xxx Rx idle reserved Rx 4FSK raw Rx 4FSK eye reserved reserved Sync Reset / abort reserved Tx idle reserved Tx 4FSK raw Tx 4FSK PRBS Tx 4FSK Preamble reserved Test Reset / abort reserved In Tx mode, the CMX7031/CMX7041 can be set to transmit data in a number of raw data modes as a data pump. The Modem Control bits should be configured in the same C-BUS write as the change in the Modem Mode bits. The Tx 4FSK raw command requires that a block of data has been loaded into the CBUS TxData registers before executing the change in the Modem Mode bits to Tx. A DataRDY IRQ will (c) 2006 CML Microsystems Plc Page 26 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 then be asserted and the host should supply a further 72 bits of payload data in the TxData registers. The CMX7031/CMX7041 will continue transmitting the payload data until the host resets the Mode bits to either Rx or IDLE, as appropriate. In Rx mode the Rx signal is routed through Input 1. Data from the host is supplied to the host through the RxData registers and should be read in response to a DataRDY IRQ. The CMX7031/CMX7041 will continue decoding the input waveform until the host resets the Mode bits to either Tx or IDLE, as appropriate. A test mode to examine the Rx "EYE" is also provided. 7.4.5 Tx Mode In Raw mode Tx operation, the pre-amble and FS1 are transmitted automatically (default values maybe changed by use of the Program Registers), and then data from the TxData Block is transmitted directly until the Mode is changed to Rx or Idle. The first block of data MUST be loaded into the TxData registers BEFORE executing the Modem Mode change to Tx. Data is transmitted MSB first. The host should write the initial data to the C-BUS TxData registers and then set the modem mode to TxRaw and the Mode bits to Tx. As soon as the data has been read from the C-BUS TxData registers the DataRDY IRQ will be asserted. (c) 2006 CML Microsystems Plc Page 27 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 note: Tx_Process This assumes that: GPIO2 and GPIO1 have been set to mode 10 (follow Mode bits) RAMDAC has been enabled Data is in 9 byte blocks Load data to C-Bus TxDataBlock transaction count =0, byte count =9 Set Modem Control toTxRaw, 4FSK, Mode = Tx note: Ensure that RAMDAC speed is fast enough to allow for hardware and internal processing delays GPIO2 and GPIO1 will change to 10 and the Modem will transmit the preamble, frame sync and data The host should ensure that any external hardware is also set into Tx mode (if not automatically controlled by the GPIO pins). note: Execute RAMDAC up No IRQ = DataRdy? yes No IRQ=Error, Modem status = Underflow may occur at note: this point, if enabled. more data to send? yes Load data to C-Bus TxDataBlock transaction count ++, byte count =9 No IRQ = TxDone? note: Due to internal processing delays in the filters etc, the Host should wait for IRQ=TxDone or implement its own delay to ensure all data has been transmitted. Yes Execute RAMDAC down Goto Rx_Process Set Modem Control to Idle, 4FSK, Mode = Idle See Rx_Process flow diagram GPIO2 and GPIO1 will change to 00 and the Modem will drop into Idle mode. The host should ensure that any external hardware is also set into Idle mode (if not automatically controlled by the GPIO pins). note: note: Goto Idle Mode Figure 13 Tx Data Flow 7.4.6 Rx Mode In Raw mode Rx operation, once a valid FS has been detected, all following data received is loaded directly into the C-BUS RxData registers. This will continue until the Mode is changed to Idle or Tx, even if there is no valid signal at the input. On exiting Rx Mode, there may be a DataRdy IRQ pending which should be cleared by the host. Note that Raw Mode operation still requires the use of a valid Frame Sync pattern in order to derive timing information for the demodulator. The device will update the C-BUS RxData registers with payload data as it becomes available, the host MUST respond to the DataRDY IRQ before the data is over-written by the modem. If "Soft" data mode has been selected, then the Payload Data in Rx mode will be coded as 4-bits of "Log Likelihood Ratio" (c) 2006 CML Microsystems Plc Page 28 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 encoded data per bit. In this mode the host must service the DataRDY IRQ at 4 times the normal rate to avoid overflow conditions. note: This assumes that: GPIO2 and GPIO1 have been set to mode 10 (follow Mode bits) RAMDAC has been enabled Data is in 9 byte blocks Rx_Process Set Modem Control to RxRaw, 4FSK, Mode = Rx note: If enabled , IRQ=FrameSync will occur before IRQ=DataRdy GPIO2 and GPIO1 will change to 01, the Modem will start to look for frame sync. The host should ensure that any external hardware is also set into Rx mode (if not automatically controlled by the GPIO pins). note: No IRQ = DataRdy? yes Load data from C-Bus RxDataBlock check transaction count and byte count No An IRQ=DataRdy may still be pending at this point note: more data to receive? yes Goto Tx_Process Set Modem Control to Idle, 4FSK, Mode = Idle See Tx_Process Flow Diagram GPIO2 and GPIO1 will change to 00, and the Modem will drop into Idle mode. The host should ensure that any external hardware is also set into Idle mode (if not automatically controlled by the GPIO pins). note: note: Goto Idle_Process Figure 14 Rx Data Flow 7.4.7 Other Modem Modes In Rx mode it is possible to output the received signal as an "EYE" diagram for test and alignment purposes. In this configuration, the filtered received signal is presented at the MOD1 pin and a trigger pulse at the MOD2 pin (derived directly from the xtal / clock source) to allow viewing on a suitable oscilloscope. In Tx mode, a fixed PRBS sequence or a fixed preamble transmission is provided which can be used for test and alignment. 7.4.8 Data Transfer The payload data is transferred to and from the host via a block of five Rx and Tx 16-bit C-BUS registers which allow up to 72 bits (9 bytes) of data to be transferred in sequence. The lowest 8 bits of the register block are reserved for a Byte Counter, Block ID and a Transaction Counter to allow the host to identify any data loss, and the remaining 72 bits hold the data to be transmitted / received. The byte count indicates how many bytes in the data block are valid and so reduces the need to perform a full 5 word CBUS read / write if only small blocks of data need to be transferred. (c) 2006 CML Microsystems Plc Page 29 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 Table 5 C-BUS Data Registers C-BUS Address $B5 $B6 $B7 $CA $CB Function Tx data 0-7 & info Tx data 8-23 Tx data 24-39 Tx data 40-55 Tx data 56-71 C-BUS address $B8 $B9 $BA $BB $C5 Function Rx data 0-7 & info Rx data 8-23 Rx data 24-39 Rx data 40-55 Rx data 56-71 The Block ID is ignored in Raw Data mode, but should be set to 01 for consistency with future enhancements. Bits 7 and 6 hold a Transaction Counter. This a two-bit counter that is incremented on every read / write of the Data Block. This is particularly useful to detect data underflow and overflow conditions. The counter increments modulo 4. The host must increment this counter on every write to the TxData block. If the CMX7031/CMX7041 identifies that a block has been written out of sequence, the Error IRQ will be asserted. The device detects that new data from the host is available by the change in the value of the Transaction Counter, therefore the host should ensure that all the data is available in the TxData block before updating this register (ie, it should be the last register the host writes to in any block transfer). In Rx mode, the CMX7031/CMX7041 will automatically increment the counter every time it writes to the RxData block, if the host identifies that a block has been written out of sequence, then it is likely that a data overflow condition has occurred and some data has been lost. 7.5 Squelch Operation Many Limiter / Discriminator chips provide a noise-quieting squelch circuit around an op amp configured as a filter. This signal is conventionally passed to a comparator to provide a digital Squelch signal, which can be routed directly to one of the CMX7031/CMX7041's GPIO pins or to the host. However with the CMX7031/CMX7041, the comparator and threshold operations can be replaced by one of the AuxADC's with programmable thresholds and hysterisis operation. The Squelch signal is signalled to the host through the Modem Status Register and can be derived from a number of sources depending on the settings in the Modem Config Register: See: o o Status - $C6 read Modem Config - $C7 write 7.6 GPIO Pin Operation The CMX7031 provides 2 GPIO pins, the CMX7041 provides 4 GPIO pins, each pin can be configured as an input or an output, and in addition, GPIO1 and 2 can be configured to reflect the Tx / Rx state of the Mode Register (TxENA and RxENA). Note that if any of these pins are configured as the Squelch Input, then it should be set as an input. See: o Modem Config - $C7 write Note that when GPIO1 and 2 are in modes 10 and 11, they will not change state until the relevant Mode change has been executed. This is to allow the host sufficient time to load the relevant data buffers and the CMX7031 time to encode the data required prior to its transmission. 7.7 Audio Tone Facility An Audio Tone Generator is provided for the host to generate keypad or alert tones. The frequency of the generator (between 300 and 3000Hz) is specified in b0:8 of the AuxData register. See: o AuxData Write - $C2 write (c) 2006 CML Microsystems Plc Page 30 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.8 Auxiliary ADC Operation The inputs to the two Auxiliary ADCs can be independently routed to any of the Signal Input pins under control of the Signal Routing register, $A7. Conversions will be performed as long as a valid input source is selected, to stop the ADCs, the input source should be set to "none". Register $C0, b6, BIAS, must be enabled for Auxiliary ADC operation. Averaging can be applied to the ADC readings by selecting the relevant bits in the Signal Routing register, $A7, the length of the averaging is determined by the value in the Programming register (P3.0 and P3.1), and defaults to a value of 1. This is a rolling average system such that a proportion of the current data will be added to the last value. The proportion is determined by the value of the average counter in P3.0 and P3.1. For an average value of 0; 50% of the current value will be applied, for a value of 1 = 25%, 2 = 12.5% etc. The maximum useful value of this field is 8. High and Low thresholds may be independently applied to both ADC channels (the comparison is applied after averaging, if this is enabled) and an IRQ generated as required (except in the case where the high threshold has been set below the low threshold). The thresholds are programmed via the AuxADC Threshold register, $B5. Auxiliary ADC data is read back in the AuxADC Data registers ($A9 and $AA) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). See: o o o o AuxADC config - $A7 write AuxADC1 data - $A9 read AuxADC2 data - $AA read AuxADC threshold data - $CD write 7.9 Auxiliary DAC / RAMDAC Operation The four Auxiliary DAC channels are programmed via the AuxDAC Control register, $A8. AuxDAC channel 1 may also be programmed to operate as a RAMDAC which will automatically output a preprogrammed profile at a programmed rate. The AuxDAC Control register, $A8, with b12 set, controls this mode of operation. The default profile is a raised cosine (see Table 8), but this may be over-written with a user defined profile by writing to Programming register P3.10. The RAMDAC operation is only available in Tx mode and, to avoid glitches in the ramp profile, it is important not to change to IDLE or Rx mode whilst the RAMDAC is still ramping. The AuxDAC outputs hold the user-programmed level during a powersave operation if left enabled, otherwise they will return to zero. Note that access to all four AuxDACs is controlled by the AuxDAC Control register, $A8, and therefore to update all AuxDACs requires four writes to this register. It is not possible to simultaneously update all four AuxDACs. See: o AuxDAC control / data - $A8 write (c) 2006 CML Microsystems Plc Page 31 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.10 Digital System Clock Generators to RF Synthesiser Ref CLK selection SysCLK1 VCO 24.57698.304MHz (49.152MHz typ) LPF VCO Ref CLK div /1 to 512 $AC b0-8 PD SysCLK1 SysCLK1 Ref Div 48 - 192kHz (96kHz typ) PLL div /1 to 1024 $AB b0-9 VCO op div /1 to 64 $AB b10-15 SysCLK1 Pre-CLK $AC b11-15 SysCLK1 Output 384kHz-20MHz LPF VCO SysCLK2 VCO 24.57698.304MHz (49.152MHz typ) Ref CLK div /1 to 512 $AE b0-8 PD SysCLK2 SysCLK2 Ref Div 48 - 192kHz (96kHz typ) PLL div /1 to 1024 $AD b0-9 VCO op div /1 to 64 $AD b10-15 SysCLK2 Pre-CLK $AE b11-15 SysCLK2 Output 384kHz-20MHz LPF VCO MainCLK VCO 24.57698.304MHz (49.152MHz typ) Ref CLK div /1 to 512 $BD b0-8 PD MainCLK MainCLK Ref Div 48 - 192kHz (96kHz typ) PLL div /1 to 1024 $BC b0-9 VCO op div /1 to 64 $BC b10-15 MainCLK Pre-CLK $BD b11-15 MainCLK Output 384kHz-50MHz (24.576MHz typ) To Internal ADC / DAC dividers OSC 4.0 - 12.288MHz Xtal or 4.0 - 24.576MHZ Clock AuxADC Div Aux_ADC (83.3kHz typ) Figure 15 Digital Clock Generation Schemes The CMX7031/CMX7041 includes a 2-pin crystal oscillator circuit. This can either be configured as an oscillator, as shown in section 5, or the XTAL input can be driven by an externally generated clock. The (c) 2006 CML Microsystems Plc Page 32 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 crystal (Xtal) source frequency can go up to 12.288MHz (clock source frequency up to 24.576MHz), but a 6.144MHz Xtal is assumed by default for the functionality provided in the CMX7031/CMX7041. (c) 2006 CML Microsystems Plc Page 33 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.10.1 System Clock Operation Two System Clock outputs, SysClock1 Out and SysClock2 Out, are available to drive additional circuits, as required. These are digital phase locked loop (PLL) clocks that can be programmed via the System Clock registers with suitable values chosen by the user. The System Clock PLL Configure registers ($AB and $AD) control the values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configure registers ($AC and $AE) control the values of the Reference Divider and signal routing configurations. The PLLs are designed for a reference frequency of 96kHz. If not required, these clocks can be independently powersaved. The clock generation scheme is shown in the block diagram of Figure 15. Note that at power-on, these pins provide, by default, a clock which is equivalent to the XTAL frequency, however in the CMX7041, the output is inhibited until enabled by a host command over the CBUS. See: o o System CLK 1 and 2 PLL data - $AB, $AD write System CLK 1 and 2 REF - $AC and $AE write 7.10.2 Main Clock Operation A digital PLL is used to create the Main Clock (nominally 24.576MHz) for the internal sections of the CMX7031/CMX7041. At the same time, other internal clocks are generated by division of either the XTAL Reference Clock or the Main Clock. These internal clocks are used for determining the sample rates and conversion times of A-to-D and D-to-A converters, running a General Purpose Timer and the signal processing block. In particular, it should be noted that in IDLE mode the setting of the GP Timer divider directly affects the C-BUS latency (with the default values this is nominally 250s). The CMX7031/CMX7041 defaults to the settings appropriate for a 6.144MHz Xtal, however if other frequencies are to be used then the Program Block registers P3.2 to P3.6 will need to be programmed appropriately at power-on. A table of common values is provided in Table 1. The C-BUS registers $BC and $BD are controlled automatically by the FI and must not be accessed directly by the user. See: o Program Block 3 - AuxDAC, RAMDAC and Clock control: 7.11 Signal Level Optimisation The internal signal processing of the CMX7031/CMX7041 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. For a device working from a 3.3V 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) - (2 x 0.3V)] Volts pk-pk = 838mV rms, assuming a sine wave signal. This should not be exceeded at any stage. 7.11.1 Transmit Path Levels For the maximum signal out of the MOD1 and MOD2 attenuators, the signal level at the output of the Modem block is set to be 0dB, The Fine Output adjustment has a maximum attenuation of 1.8dB and no gain, whereas the Coarse Output adjustment has a variable attenuation of up to +44.8dB and no gain. 7.11.2 Receive Path Levels The Fine Input adjustment has a maximum attenuation of 3.5dB and no gain, whereas the Coarse Input adjustment has a variable gain of up to +22.4dB and no attenuation. With the lowest gain setting (0dB), the maximum allowable input signal level at the DiscFB pin would be 883mV rms. This signal level is an absolute maximum, which should not be exceeded anywhere in the signal processing chain if severe distortion is to be avoided. 7.12 Tx Spectrum Plots The following figures show the Tx spectrum when using a suitable signal generator as measured on a spectrum analyser. In both cases the internal PRBS generator was used. Note that the I&Q mode is (c) 2006 CML Microsystems Plc Page 34 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 sensitive to variations in DC offset in the modulation path and these must be minimised to keep the residual AM to an acceptable level. RBW Ref Lvl -18 dBm -18 500 Hz 2 kHz 700 ms RF Att 10 dB Marker 1 [T1] Ref Lvl -18 dBm -18 RBW -76.30 dBm 446.09631250 MHz VBW SWT 500 Hz 2 kHz 700 ms RF Att 10 dB Marker 1 [T1] -75.85 dBm 446.09631250 MHz VBW SWT Unit dBm Unit dBm 1 [T1] -30 -75.85 dBm 446.09631250 MHz A 1 [T1] -76.30 dBm 446.09631250 MHz A CH PWR ACP Up -21.19 dBm -66.25 dB -67.42 dB -83.63 dB -84.58 dB 1SA -30 CH PWR ACP Up ACP Low -22.02 dBm -63.35 dB -67.65 dB -74.93 dB -74.22 dB 1RM -40 ACP Low ALT1 Up ALT1 Low -40 ALT1 Up ALT1 Low -50 1VIEW -50 1VIEW -60 -60 -70 -70 1 -80 -80 1 -90 cu2 cu2 cu1 -90 cu2 cu2 cu1 -100 cu1 C0 C0 cl1 -100 cu1 C0 C0 cl1 -110 cl1 cl2 cl2 -110 cl1 cl2 cl2 -118 Center 446.1 MHz Date: 2.OCT.2006 13:45:44 3.5 kHz/ Span 35 kHz -118 Center 446.1 MHz 3.5 kH z/ 13:30:09 Span 35 kHz Date: 2.OCT.2006 2-point modulation spectrum I&Q modulation spectrum Figure 16 Tx Modulation Spectra - 4800bps Marker 1 [T1] RBW VBW SWT 500 Hz 2 kHz 1.2 s 1 [T1] RF Att 10 dB Ref Lvl Marker 1 [T1] -29.87 dBm 446.10018913 MHz -18 RB W VBW SWT 500 Hz 2 kHz 1.4 s RF Att 10 dB Ref Lvl -18 dBm -18 -44.69 dBm 446.09631250 MHz Unit dBm -44.69 dBm -18 dBm Unit dBm A 1 [T1] -30 -29.87 dBm 446.10018913 MHz A 446.09631250 MHz -30 CH PWR ACP Up ACP Low -21.53 dBm -74.16 dB -71.46 dB -80.62 dB -81.36 dB 1SA 1 CH PWR ACP Up -22.04 dBm -67.21 dB -68.57 dB -76.83 dB -76.65 dB 1RM -40 1 -50 ALT1 Up ALT1 Low -40 ACP Low ALT1 Up ALT1 Low -50 -60 -60 -70 -70 -80 -80 -90 cu2 cu2 cu1 cu1 -90 C0 C0 cl2 -100 C0 C0 cl1 cl2 -100 cl1 cl1 -110 cl1 cl2 cl2 -110 cu1 cu1 cu2 cu2 -118 -118 Center 446.1 MHz Date: 9.OCT.2006 10:27:50 6 kHz/ Span 60 kHz Date: Center 446.1 MH z 9.OCT.2006 09:22:44 7 kHz/ Span 70 kHz 2-point modulation spectrum I&Q modulation spectrum Figure 17 Tx Modulation Spectra - 9600bps (c) 2006 CML Microsystems Plc Page 35 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 7.13 C-BUS Register Summary Table 6 C-BUS Registers ADDR. (hex) $01 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B7 $B8 $B9 $BA $BB $BC $BD $BE $BF $C0 $C1 $C2 $C3 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF REGISTER W W W R R W W W W W W C-BUS RESET AuxADC Config AuxDAC Data and Control AuxADC1 Data and Status / Checksum 2 hi AuxADC2 Data and Status / Checksum 2 lo System Clk 1 PLL configure System Clk 1 Ref configure System Clk 2 PLL configure System Clk 2 Ref configure Reserved Analog Output Gain Input Gain and Signal Routing Reserved Reserved Reserved TxData 0 TxData 1 TxData 2 RxData 0 / Checksum 1 hi RxData 1 / Checksum 1 lo RxData 2 RxData 3 Main CLK PLL configure - reserved Main CLK Ref configure - reserved Reserved Reserved Power-Down Control Mode Control AuxData write Reserved Rx Data 4 IRQ Status Modem Config Programming Register Modem Status Tx Data 3 Tx Data 4 AuxData read AuxADC Thresholds Interrupt Mask Reserved Word Size (bits) 0 16 16 16 16 16 16 16 16 16 16 W W W R R R R W W 16 16 16 16 16 16 16 16 16 W W W R R W W R W W R W W 16 16 16 16 16 16 16 16 16 16 16 16 16 All other C-BUS addresses (including those not listed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation. (c) 2006 CML Microsystems Plc Page 36 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8 8.1 Performance Specification Electrical Performance 8.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -0.3 -0.3 -30 -20 0 0 Max. 4.5 4.5 DVDD + 0.3 AVDD + 0.3 +30 +20 0.3 50 Unit V V V V mA mA V mV Supply: DVDD- DVSS AVDD- AVSS Voltage on any pin to DVSS Voltage on any pin to AVSS Current into or out of any power supply pin (excluding VBIAS) ( i.e. VDEC, AVDD, AVSS, DVDD or DVSS) Current into or out of any other pin Voltage differential between power supplies: DVDD and AVDD DVSS and AVSS L9 Package (64-pin LQFP) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. - - -55 -40 Max. 668 6 +125 +85 Unit mW mW/C C C Q1 Package (64-pin VQFN) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. - - -55 -40 Max. 1410 14 +125 +85 Unit mW mW/C C C L4 Package (48-pin LQFP) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. - - -55 -40 Max. 668 6 +125 +85 Unit mW mW/C C C Q3 Package (48-pin VQFN) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. - - -55 -40 Max. 1410 14 +125 +85 Unit mW mW/C C C (c) 2006 CML Microsystems Plc Page 37 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply Voltage: DVDD - DVSS AVDD - AVSS VDEC - DVSS Operating Temperature XTAL/CLK Frequency (using a Xtal) XTAL/CLK Frequency (using an external clock) Min. 3.0 3.0 2.25 -40 4.0 4.0 Max. 3.6 3.6 2.75 +85 12.288 24.576 Unit V V V C MHz MHz 12 11 11 Notes: 11 12 Nominal XTAL/CLK frequency is 6.144MHz. The VDEC supply is automatically derived from DVDD by the on-chip voltage regulator. (c) 2006 CML Microsystems Plc Page 38 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8.1.3 Operating Characteristics For the following conditions unless otherwise specified: External components as recommended in Figure 4. Maximum load on digital outputs = 30pF. Xtal Frequency = 6.144MHz 0.01% (100ppm); Tamb = -40C to +85C. AVDD = DVDD = 3.3V. VDEC = 2.5V Reference Signal Level = 308mV rms at 1kHz with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Signal to Noise Ratio (SNR) in bit rate bandwidth. Input stage gain = 0dB. Output stage attenuation = 0dB. Current consumption figures quoted in this section apply to the device when loaded with FI 2.0 only. The use of other Function ImagesTM, can modify the current consumption of the device. DC Parameters Supply Current All Powersaved DIDD AIDD IDLE Mode DIDD AIDD Rx Mode DIDD (4800bps - search for FS) DIDD (9600bps - search for FS) DIDD (4800bps - FS found) DIDD (9600bps - FS found) AIDD Tx Mode DIDD (4800bps - 2-point) DIDD (9600bps - 2-point) DIDD (4800bps - I&Q) DIDD (9600bps - I&Q) AIDD (AVDD = 3.3V) Additional current for each Auxiliary System Clock (output running at 4MHz) DIDD (DVDD = 3.3V, VDEC = 2.5V) Additional current for each Auxiliary ADC DIDD (DVDD = 3.3V, VDEC = 2.5V) Additional current for each Auxiliary DAC AIDD (AVDD = 3.3V) Notes: 21 22 23 Notes 21 - - 22 23 22 - - - - - - - 22 - - - - - 4.3 5.2 5.4 7.3 1.5 TBD TBD TBD TBD TBD mA mA mA mA mA 1.4 1.6 4.7 7.5 2.8 3.7 1.6 TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA 8 4 100 20 A A Min. Typ. Max. Unit - - - 250 50 200 - - - A A A Not including any current drawn from the device pins by external circuitry. System Clocks, Auxiliary circuits disabled, but all other digital circuits (including the Main Clock PLL) enabled. May be further reduced by power-saving unused sections (c) 2006 CML Microsystems Plc Page 39 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 DC Parameters (continued) XTAL/CLK Input Logic `1' Input Logic `0' Input current (Vin = DVDD) Input current (Vin = DVSS) C-BUS Interface and Logic Inputs Input Logic `1' Input Logic `0' Input Leakage Current (Logic `1' or `0') Input Capacitance C-BUS Interface and Logic Outputs (IOH = 120A) Output Logic `1' (IOH = 1mA) Output Logic `0' (IOL = 360A) (IOL = -1.5mA) "Off" State Leakage Current IRQN (Vout = DVDD) REPLY_DATA (output HiZ) VBIAS Output voltage offset wrt AVDD/2 (IOL < 1A) Output impedance Notes 25 Min. Typ. Max. Unit 70% - - -40 - - - - - 30% 40 - DVDD DVDD A A 70% - -1.0 - - - - - - 30% 1.0 7.5 DVDD DVDD A pF 90% 80% - - - -1.0 -1.0 26 - - - - - - - - - - - 10% 15 % 10 +1.0 +1.0 DVDD DVDD DVDD DVDD A A A 2% 22 - - AVDD k Notes: 25 26 Characteristics when driving the XTAL/CLK pin with an external clock source. Applies when utilising VBIAS to provide a reference voltage to other parts of the system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must always be decoupled with a capacitor as shown in Figure 4. (c) 2006 CML Microsystems Plc Page 40 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 AC Parameters XTAL/CLK Input 'High' pulse width 'Low' pulse width Input impedance (at 6.144MHz) Resistance Powered-up Capacitance Resistance Powered-down Capacitance Xtal start up (from powersave) Auxiliary System Clk 1/2 Outputs XTAL/CLK input to CLOCK_OUT timing: (in high to out high) (in low to out low) 'High' pulse width 'Low' pulse width VBIAS Start up time (from powersave) Microphone, Alternative and Discriminator Inputs (MIC, ALT, DISC) Input impedance Maximum Input Level (pk-pk) Load resistance (feedback pins) Amplifier open loop voltage gain (I/P = 1mV rms at 100Hz) Unity gain bandwidth Programmable Input Gain Stage Gain (at 0dB) Cumulative Gain Error (wrt attenuation at 0dB) Notes Min. Typ. Max. Unit 31 31 15 15 - - - - - - - 150 20 300 20 400 - - - - - - - ns ns k pF k pF ms 32 32 33 33 - - 76 76 15 15 81.38 81.38 - - 87 87 ns ns ns ns - 30 - ms 34 35 - - 80 - - 1 - - 60 1.0 - 80% - - - M AVDD k dB MHz 36 37 37 -0.5 -1.0 0 0 +0.5 +1.0 dB dB Notes: 31 32 33 34 35 36 37 Timing for an external input to the XTAL/CLK pin. XTAL/CLK input driven by an external source. 6.144MHz XTAL fitted and 6.144MHz output selected. With no external components connected Centered about AVDD/2; after multiplying by the gain of input circuit (with external components connected). Gain applied to signal at output of buffer amplifier: DiscFB, AltFB or MicFB Design Value. Overall attenuation input to output has a tolerance of 0dB 1.0dB (c) 2006 CML Microsystems Plc Page 41 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 AC Parameters Modulator Outputs 1/2 and Audio Output (MOD 1, MOD 2, AUDIO) Power-up to output stable Modulator Attenuators Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Output current range (AVDD = 3.3V) Output voltage range Load resistance Audio Attenuator Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Output current range (AVDD = 3.3V) Output voltage range Load resistance Notes Min. Typ. Max. Unit 41 43 - -1.0 -0.6 - - - 0.5 20 -1.0 -1.0 - - - 0.5 20 50 0 0 600 500 - - - 0 0 600 500 - - - 100 +1.0 +0.6 - - 125 AVDD -0.5 - +1.0 +1.0 - - 125 AVDD -0.5 - s dB dB k A V k dB dB k A V k 42 42 44 43 42 42 44 Notes: 41 42 43 44 Power-up refers to issuing a C-BUS command to turn on an output. These limits apply only if VBIAS is on and stable. At power supply switch-on, the default state is for all blocks, except the XTAL and C-BUS interface, to be in placed in powersave mode. Small signal impedance, at AVDD = 3.3V and Tamb = 25C. With respect to the signal at the feedback pin of the selected input port. Centered about AVDD/2; with respect to the output driving a 20k load to AVDD/2. (c) 2006 CML Microsystems Plc Page 42 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 AC Parameters (cont.) Auxiliary Signal Inputs (Aux ADC 1 to 4) Source Output Impedance Auxiliary 10 Bit ADCs Resolution Maximum Input Level (pk-pk) Conversion time Input impedance Resistance Capacitance Zero error (input offset to give ADC output = 0) Integral Non-linearity Differential Non-linearity Auxiliary 10 Bit DACs Resolution Maximum Output Level (pk-pk), no load Zero error (output offset from a DAC input = 0) Resistive Load Integral Non-linearity Differential Non-linearity Notes Min. Typ. Max. Unit 51 - - 24 k 54 52 - - - - - 10 - 62.4 10 5 - - - - 80% - - - 10 3 1 Bits AVDD s M pF mV LSBs LSBs 53 0 - - 54 - 80% 0 5 - - 10 - - - - - - - 10 - 4 1 Bits AVDD mV k LSBs LSBs 53 Notes: 51 52 53 54 Denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. With an auxiliary clock frequency of 6.144MHz. Guaranteed monotonic with no missing codes. Centred about AVDD/2. (c) 2006 CML Microsystems Plc Page 43 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 AC Parameters (cont.) Reference Clock Input Input Logic `1' Input Logic `0' Frequency Divide ratios (R) Notes: 62 63 Notes Min. Typ. Max. Unit 62 62 63 70% - 5.0 1 - - 19.2 - - 30% 40.0 8192 VDD VDD MHz Square wave input. Separate dividers provided for each PLL. (c) 2006 CML Microsystems Plc Page 44 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8.1.4 Parametric Performance For the following conditions unless otherwise specified: External components as recommended in Figure 4. Maximum load on digital outputs = 30pF. Xtal Frequency = 6.144MHz 0.01% (100ppm) ); Tamb = -40C to +85C. AVDD = DVDD = 3.0V to 3.6V. Reference Signal Level = 308mV rms at 1kHz with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Signal to Noise Ratio (SNR) in bit rate bandwidth. Input stage gain = 0dB, Output stage attenuation = 0dB. All figures quoted in this section apply to the device when loaded with FI 2.0 only. The use of other Function ImagesTM, can modify the parametric performance of the device. AC Parameters (cont.) Modem symbol rate Modulation Filter RRC alpha Tx mod accuracy Tx bit rate accuracy Tx output level (MOD1, MOD2, 2-point) Tx output level (MOD1, MOD2, I&Q) Tx adjacent channel power (MOD1, MOD2, prbs) Rx sensitivity (BER 2400 sym s-1) Rx sensitivity (BER 4800 sym s-1) Rx co-channel rejection Rx input level Rx input DC offset Notes: 64 65 66 Notes Min. 2400 Typ. 4-FSK 0.2 % RMS ppm Vpk-pk Vpk-pk dB Max. 4800 Unit sym s-1 64 64 65 66 66 2.88 2.20 -60 10 0.5 838 Vdd-0.5 dB mVrms V Transmitting continuous default preamble Measured as per EN 301 166 or EN300 113 as appropriate Measured at base-band - radio design will affect ultimate product performance (c) 2006 CML Microsystems Plc Page 45 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8.2 C-BUS Timing Figure 18 C-BUS Timing C-BUS Timing tCSE CSN Enable to SClk high time tCSH Last SClk high to CSN high time SClk low to ReplyData Output Enable tLOZ Time tHIZ CSN high to ReplyData high impedance CSN high time between transactions tCSOFF tNXT Inter-byte time SClk cycle time tCK SClk high time tCH tCL SClk low time Command Data setup time tCDS Command Data hold time tCDH tRDS Reply Data setup time Reply Data hold time tRDH Notes Min. 100 100 0.0 - 1.0 200 200 100 100 75 25 50 0 Typ. - - - - - - - - - - - - - Max. - - - 1.0 - - - - - - - - - Unit ns ns ns s s ns ns ns ns ns ns ns ns Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge. 3. Commands are acted upon at the end of each command (rising edge of CSN). 4. To allow for differing C serial interface formats C-BUS compatible ICs are able to work with SERIAL_CLOCK pulses starting and ending at either polarity. 5. Maximum 30pF load on IRQN pin and each C-BUS interface line. (c) 2006 CML Microsystems Plc Page 46 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS timing specification. The CMX7032/CMX7041 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints. (c) 2006 CML Microsystems Plc Page 47 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 8.3 Packaging DIM. MIN. TYP. 9.00 BSC 9.00 BSC 0.80 7.00 7.00 1.00 7.95 7.95 MAX. * * A B C F G G1 H J L M P T Y NOTE : 0.225 0.00 0.18 0.30 0.05 0.30 0.50 0.75 0.50 0.20 0 12 * A & B are reference data and do not include mold deflash or protrusions. All dimensions in mm Angles are in degrees Index Area 1 Index Area 2 Exposed Metal Pad Dot Dot Chamfer Index Area 1 is located directly above Index Area 2 The underside of the package has an exposed metal pad which can be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also be required Figure 19 Mechanical outline for 64-pad VQFN (Q1) Order as part no. CMX7031Q1 Figure 20 Mechanical outline for 64-pin LQFP (L9) Order as part no. CMX7031L9 (c) 2006 CML Microsystems Plc Page 48 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 DIM. MIN. TYP. 7.00 BSC 7.00 BSC MAX. * * A B C F G G1 H J L M P T Y NOTE : 0.80 2.75 2.75 1.00 5.25 5.25 0.225 0.00 0.18 0.30 0.05 0.30 0.50 0.75 0.50 0.20 0 12 * A & B are reference data and do not include mold deflash or protrusions. All dimensions in mm Angles are in degrees Index Area 1 Index Area 2 Exposed Metal Pad Dot Dot Chamfer Index Area 1 is located directly above Index Area 2 The underside of the package has an exposed metal pad which can be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also be required Figure 21 Mechanical Outline of 48-pin VQFN (Q3) Order as part no. CMX7041Q3 Figure 22 Mechanical Outline of 48-pin LQFP (L4) Order as part no. CMX7041L4 (c) 2006 CML Microsystems Plc Page 49 D/7031/41_FI2.0/1 4FSK Radio Processor CMX7031/CMX7041 About FirmASIC(R) CML's proprietary FirmASIC(R) component technology reduces cost, time to market and development risk, with increased flexibility for the designer and end application. FirmASIC(R) combines Analogue, Digital, Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. Specific functions of a FirmASIC(R) device are determined by uploading its Function ImageTM during device initialization. New Function ImagesTM may be later provided to supplement and enhance device functions, expanding or modifying end-product features without the need for expensive and time-consuming design changes. FirmASIC(R) devices provide significant time to market and commercial benefits over Custom ASIC, Structured ASIC, FPGA and DSP solutions. They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products (ASSP's). Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. www.cmlmicro.com For FAQs see: www.cmlmicro.com/products/faqs/ For a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm For detailed application notes: www.cmlmicro.com/products/applications/ Oval Park, Langford, Maldon, Essex, CM9 6WG - England. 4800 Bethania Station Road, Winston-Salem, NC 27105 - USA. No 2 Kallang Pudding Road, #09 - 05/06 Mactech Industrial Building, Singapore 349307 No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. Tel: +86 21 6317 4107 +86 21 6317 8916 Fax: +86 21 6317 0243 Sales: cn.sales@cmlmicro.com.cn Technical Support: sg.techsupport@cmlmicro.com Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 Sales: sales@cmlmicro.com Technical Support: techsupport@cmlmicro.com Tel: +1 336 744 5050, 800 638 5577 Fax: +1 336 744 5054 Sales: us.sales@cmlmicro.com Technical Support: us.techsupport@cmlmicro.com Tel: +65 6745 0426 Fax: +65 6745 2917 Sales: sg.sales@cmlmicro.com Technical Support: sg.techsupport@cmlmicro.com (c) 2006 CML Microsystems Plc Page 50 D/7031/41_FI2.0/1 |
Price & Availability of CMX7031
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |